Tracing the Silicon: Google’s TPU Shift to Samsung 2nm – A Supply Chain Fork
The data suggests Google is moving a critical piece of its next-generation TPU, codenamed “Icefish,” from TSMC’s 5nm to Samsung’s 2nm GAA process. The narrative peddled by press releases is about performance gains. The numbers tell a different story: this is a supply chain hedge, not a performance breakout.
Context: Google’s TPU architecture has long been fabbed exclusively by TSMC, with Broadcom handling the design integration. The Icefish chip—the successor to the v5p—is the first to split its key matrix compute unit to a different foundry. Samsung’s SF2 node is its first Gate-All-Around (GAA) process, promising lower leakage and higher drive current compared to FinFET. But GAA is unproven at high volume. The industry has scars from Samsung’s 7nm yield disasters. Yet Google is betting on Samsung’s 2nm for the heart of its AI inference engine.
Core: Let’s trace the logic. Why Samsung? Not because of superior performance. Benchmarks from other chips on SF2 are not yet public. The real incentive is diversification. TSMC’s capacity is stretched across NVIDIA, AMD, Apple, and Intel. Relying solely on TSMC for the TPU creates a single point of failure—a centralization risk that any systems engineer would flag. In my 2020 audit of MakerDAO’s CDP system, I stress-tested liquidation cascades under oracle failures. The lesson was identical: a single source of truth creates a critical vector. Here, the oracle is TSMC’s fab allocation.
From a cost perspective, the shift makes sense. Electricity is the dominant operational cost in data centers. A 40% improvement in performance-per-watt from a node shrink directly lowers the cost per inference. Google can pass that savings to its Cloud TPU customers or undercut competitors. But the trade-off is subtle. Samsung’s 2nm GAA requires new design rules, new IP, and new verification flows. The re-engineering cost is non-trivial. Google is not just swapping foundries; it is rewriting the physical design. That introduces schedule risk.
Tracing the silent logic where value meets code. The term “key components” in the official leak is deliberately vague. It implies a modular chiplet design. The compute die—the matrix engine—may be on Samsung 2nm, while the I/O and memory interfaces stay on a mature TSMC node. This is a smart hedge: it isolates the high-risk process change to the core and keeps the rest stable. But it also introduces inter-die latency and voltage mismatches. The engineering complexity is higher than a monolithic shift.
Now the contrarian angle. The real blind spot is not yield; it is the assumption that a second foundry solves the dependency problem. Google is swapping one single source (TSMC) for another single source (Samsung) for the compute tile. If Samsung faces its own yield crisis or geopolitical disruption, the chip is stuck. The supply chain is still a single line, just a different letter. The true solution would be a multi-foundry strategy where multiple vendors produce the same design—but that is mathematically and economically infeasible for a proprietary ASIC. The industry has not solved this. Bitcoin miners tried similar multi-sourcing for ASIC production with similar failures.
Furthermore, the performance uplift from 2nm GAA may be marginal due to thermal density limits. As transistors shrink, power density rises, and cooling becomes the bottleneck. Google’s TPU racks already use liquid cooling. Doubling down on process advance without rethinking chip architecture (e.g., near-memory compute) yields diminishing returns. NVIDIA’s B200 uses a different strategy: two dies on a single package with large interconnects. Google is betting on transistor scaling while others bet on packaging. Which vector is more robust? The data points to packaging innovations yielding higher gains in the next two generations.
I do not trust the doc; I trust the trace. The official story is about efficiency. The subtext is a desperate effort to control margin and capacity. Google’s own workload—mostly inference for Gemini and search—scales linearly with compute. If Samsung’s 2nm fails to ramp by 2025, Google faces a capacity cliff. It cannot simply order more from TSMC because the design is already committed to Samsung’s process. The re-spin time is 12-18 months.
Dissecting the corpse of a failed standard. If Samsung’s GAA yields are sub-50%, the Icefish chip will be delayed. Google’s Cloud TPU roadmap will slip, giving NVIDIA and AMD more time to lock in enterprise contracts. The risk is real. Samsung’s 3nm GAA was used only in its own Exynos chips and a few low-volume designs. 2nm is the first attempt at a high-volume, high-performance client foundry node. The probability of yield disruption is not negligible.
Behind the collateral lies a maze of incentives. The collateral here is Google’s entire AI service revenue. If the chip fails, the cloud business suffers. The incentive to push a premature process to market is high. There is a parallel to algorithmic stablecoins: the seigniorage model looked great on paper but collapsed under real-world volatility. The same applies to unproven GAA at scale.
Takeaway: The Google-Samsung alliance is a defensive play, not an offensive one. It buys optionality but introduces execution uncertainty. For investors and developers relying on Google Cloud’s AI offerings, the timeline is now a function of Samsung’s fab yield, not just Google’s architecture. I will be tracking whispers from the HVM line in Hwaseong. The first tape-out results will tell more than any keynote.
I trust the trace, not the press release.